Exemplary embodiments relate to a method of performing a program verification operation using a page buffer of a nonvolatile memory device and, more particularly, to the page buffer of a nonvolatile memory device and a method of performing a program verification operation using the same, which are capable of reducing the consumption of current by controlling a bit line precharge operation during a program verification operation performed on program-inhibited cells.
There has been an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and which do not require the refresh function of rewriting data at specific intervals. Here, the term ‘program’ refers to an operation of writing data into a memory cell.
To increase the degree of integration of memory devices, there has been developed a NAND type flash memory device in which a number of memory cells are coupled in series together (the drain or the source of a transistor contained in each cell is shared by neighboring memory cells), thus forming one string. The NAND type flash memory device, unlike a NOR type flash memory device, is a memory device configured to sequentially read information.
FIG. 1 is a diagram illustrating a page buffer of a known nonvolatile memory device and a method of performing a program verification operation using the same.
Referring to FIG. 1, a sense node SO is precharged to a high voltage level using a precharge unit 20. The sense node SO and a bit line BL are coupled together using a bit line selection unit 10. Thus, the bit line BL is also precharged to a high voltage level ({circle around (1)}). Here, a verification voltage is supplied to a memory cell selected from a number of memory cells coupled to the bit line BL, and a pass voltage is supplied to the remaining unselected memory cells. If the selected memory cell is programmed to have an increased threshold voltage, the corresponding memory cell becomes an off-cell, and so the bit line BL coupled to the selected memory cell maintains the high voltage level. However, if the selected memory cell has not yet been programmed, the precharged bit line BL is discharged by an evaluation operation, and so the sense node SO is discharged to a low voltage level. Next, the precharge or discharge state of the sense node SO is sensed using a second latch unit 40, and a verification operation is then performed ({circle around (2)}).
In the program verification operation using the known page buffer, if the selected memory cell is a program-inhibited cell that should maintain an erase state, the bit line BL precharged to a high voltage level is discharged during the evaluation operation. Accordingly, if a number of program-inhibited cells exist within one page, the amount of current discharged is increased. An excessive increase in the amount of discharged current causes a malfunction of the device and requires a number of the sense nodes SO and the bit lines to be always precharged. It leads to an increase in the consumption of current during a program verification operation.